1. Field of the Invention
The present invention relates to a delay control circuit for introducing an arbitrary delay into a signal.
2. Description of the Related Art
Generally, there are two ways below for introducing the arbitrary delay (or an arbitrary phase difference) into a clock signal or the like.    (1) PLL (Phase Locked Loop) or DLL (Delay Locked Loop)    (2) Buffer for desired delay
The Patent Document 1 below discloses a variable delay circuit for controlling a delay time by changing a gate capacity of a transistor which is parallelly connected to a transmission path of a signal. The Patent Document 2 discloses a DLL circuit which is used for a memory device. The Patent Document 3 discloses a highly accurate PLL circuit. The Patent Document 4 discloses a synchronous type semiconductor memory device including the DLL circuit.    Patent Document 1            Japanese Patent Application Publication No. 11-055091            Patent Document 2            Japanese Patent Application Publication No. 2003-203481            Patent Document 3            Japanese Patent Application Publication No. 2004-208152            Patent Document 4            Japanese Patent Application Publication No. 2002-230972        
In the conventional techniques of the PLL and DLL, although a highly accurate control is realized, the circuit area is large and the power consumption is high in the case of implementation as an analog circuit. Also, an external terminal may be required for a capacitor or the like prepared externally. A delay buffer can be manufactured easily, however, the accuracy is lowered than in the case of the PLL and the DLL.
When it is desired to introduce the arbitrary delay, especially a highly accurate and relatively large delay, into the clock signal in a conventional technique, it is difficult to realize a configuration of a small area and low power consumption simultaneously.